Ethernet Switch IP cores
The above diagram shows one possible Ethernet switch that can be configured from the
ChipEnet Ethernet switch IP core. The switch is scalable in the number of ports and the
size of the queues. Some key characteristics are:
The switch IP core can be implemented in small Spartan 3 FPGAs, even with Gigabit ports.
ChipEnet Ethernet switch IP core. The switch is scalable in the number of ports and the
size of the queues. Some key characteristics are:
- 10/100 Mbit and Gigabit ports
- Cut through architecture - switch delay as low as 150ns
- Optional packet parsing logic to support IEEE 1588 and other protocols
- Optional packet priority based on packet parameters - address, type
- Optional custom port interface - port can interface directly to processor
- Optional IEEE 1588 support
- Managed and unmanaged versions
- VLAN, STP/RSTP support
- Optional statistics gathering
The switch IP core can be implemented in small Spartan 3 FPGAs, even with Gigabit ports.
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