Services

ChipEnet IP cores have been extensively tested in hardware using
application level software. The cores are designed to have simple interfaces
that are easy to connect to. Interface timing and clocking are synchronous
and as tolerant as possible. Documentation are written to be clear and
complete. Self contained diagnostic logic are provided to allow quick
verification of functionality in your FPGA system.

Our goal is to make usage of ChipEnet IP cores quick and easy.

We don't expect the average user to require extensive support. After all,
the interface is just a FIFO. However, if you do need help, you will be
assisted from the initial contact by the designer of the core rather than
someone reading from a help desk script.

Support is provided for 1 year by email or phone. Please include a complete
description of the problem and complete contact information. If possible,
include a VCD file, less than 10MB in size, showing only the IP core interface
signals.

Support is on a best effort basis. We cannot guarantee solutions to all
possible problems because we don't have complete control over the entire
FPGA design. Some problems, such as signal integrity or software threads
synchronization, are extremely difficult to resolve. However, we do have a
lot of experience with such problems so we can help.

Onsite consultation is available. Please email info@chipenet.com for a quote.

ChipEnet IP cores may also be customized. If you have special needs, let us
know. You might be surprised at how quickly we can make changes and
how reasonable the costs are.