10/100 Mbit and Gigabit Ethernet MAC IP cores for Xilinx FPGAs
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
The ChipEnet family of Ethernet MAC cores add Ethernet interface/networking capability to FPGAs and can be
implemented in any Xilinx FPGAs. The MAC cores will run at 125MHz even in the slow speed grades. The cores
are scalable with respect to FIFO size and can have any type of user logic interface required. The user logic
interface operates in the user clock domain and the PHY interface runs in the PHY clock domains.
The MAC cores have a very simple default FIFO interface and directly drive an external PHY. To send a packet,
just write into the FIFO and send. The MAC prepends the header, the CRC is calculated and appended to the
end of the data bytes per IEEE 802.3 specification. To receive a packet, just read from the FIFO when the
status flag indicate packet available. The MAC core directly drive a standard 10/100 Mb/s PHY or 1000Mb/s
PHY. With this Ethernet connection it becomes easy to talk to the FPGA from a normal PC. Initialization,
control and data transfer to/from the FPGA can be easily done with a simple program running on a PC. The
user is free to define any protocol desired to be transferred by the Ethernet packets. This allows the
maximum freedom in defining the FPGA architecture.
The basic MAC cores come in two types with two speeds each. The two speeds are 10/100 Mb and Gigabit.
The two types are streaming data and block data. Streaming data MACs are designed to send or receive
packets as soon as data is available, without waiting for all of the data to be written into the FIFOs. Received
packets are available immediately with status bits to indicate packet start, end, and CRC error. Packets may be
sent with specified inter-packet gaps and transmission started as soon as desired, before all data is written
into the send Fifo. Block data MACs wait for all of the data to be written into the FIFOs before sending the
packet or announcing the availability of received packets. Header address bytes and CRC bytes are optionally
made available. Packets can also be deleted if CRC errors occur or if the header address does not match.
There are many variations possible in the configuration of MAC IP cores, please inquire.
implemented in any Xilinx FPGAs. The MAC cores will run at 125MHz even in the slow speed grades. The cores
are scalable with respect to FIFO size and can have any type of user logic interface required. The user logic
interface operates in the user clock domain and the PHY interface runs in the PHY clock domains.
The MAC cores have a very simple default FIFO interface and directly drive an external PHY. To send a packet,
just write into the FIFO and send. The MAC prepends the header, the CRC is calculated and appended to the
end of the data bytes per IEEE 802.3 specification. To receive a packet, just read from the FIFO when the
status flag indicate packet available. The MAC core directly drive a standard 10/100 Mb/s PHY or 1000Mb/s
PHY. With this Ethernet connection it becomes easy to talk to the FPGA from a normal PC. Initialization,
control and data transfer to/from the FPGA can be easily done with a simple program running on a PC. The
user is free to define any protocol desired to be transferred by the Ethernet packets. This allows the
maximum freedom in defining the FPGA architecture.
The basic MAC cores come in two types with two speeds each. The two speeds are 10/100 Mb and Gigabit.
The two types are streaming data and block data. Streaming data MACs are designed to send or receive
packets as soon as data is available, without waiting for all of the data to be written into the FIFOs. Received
packets are available immediately with status bits to indicate packet start, end, and CRC error. Packets may be
sent with specified inter-packet gaps and transmission started as soon as desired, before all data is written
into the send Fifo. Block data MACs wait for all of the data to be written into the FIFOs before sending the
packet or announcing the availability of received packets. Header address bytes and CRC bytes are optionally
made available. Packets can also be deleted if CRC errors occur or if the header address does not match.
There are many variations possible in the configuration of MAC IP cores, please inquire.
- Conforms to IEEE 802.3-2002 specification, 100Base-TX, 1000BASE-TX full duplex.
- Interfaces to standard PHYs with 4/8 bit wide data busses, MII, SGMII.
- Optional unlimited receive packet size.
- Optional source address extraction.
- Optional receive packet CRC bytes extraction.
- Very simple send & receive FIFO interface, SPI Interface .
- Support Multicast, Broadcast. No restrictions on type field.
- No MII management interface needed.
- Pass through MAC control frames.
Up to 250 MBytes/second of full duplex bandwidth !!!