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The ChipEnet family of Ethernet MAC cores add Ethernet interface/networking
capability to a FPGA and are designed to have the lowest possible gate count for the
feature set. The design goals are to reduce the footprint as much as possible and
have simple interfaces which matches the type of data being sent or received. Low
gate or LUT count is needed to reduce the usage of precious FPGA resources, reduce
the design iteration time and to speed up the FPGA programming process.

The MAC cores have a very simple FIFO interface and also directly drive an external
PHY. To send a packet, just write into the FIFO and send. The MAC performs the
header is appended, the CRC calculated and appended to the end of the data bytes
per IEEE 802.3 specification. To receive a packet, just read from the FIFO when not
empty. The MAC core directly drive a standard 100Mb/s PHY or 1000Mb/s PHY. With
this Ethernet connection it becomes easy to talk to the FPGA from a normal PC.
Initialization, control and data transfer to/from the FPGA can be easily done with a
simple program running on a PC. The user is free to define any protocol desired to
be transferred by the Ethernet packets. This allows the maximum freedom in
defining the FPGA architecture.

The MAC cores come in 2 speeds with 2 different Fifo sizes. The 2 speeds are
100Mb/s and Gigabit. The smaller Fifo version does not use any BLOCK RAMs and
has 128 byte Fifos. The larger Fifo version use 2 BLOCK RAMs and has 2K byte Fifos.
Both Fifo versions have independent Fifos for the send and receive logic.

The Fifo size does not necessarily limit the size of the packet which can be sent or
received. A 128 byte Fifo MAC can send or receive a 1500 byte packet or even a
10,000 byte packet. But obviously, large received packets must be read out of the
receive Fifo fairly quickly and large sent data packets must be written into the send
Fifo at a rate which matches the transmission rate. A packet small enough to fit in
the Fifo may be read out or transmitted more leisurely.

The smallMACs, sm1000 & sm100, are intended for random packet reception or
transmission. These MACs will optionally delete received packets with CRC errors or
mismatched destination addresses. The CRC bytes may also be optionally read out.
Byte count of transmitted packets may be optionally inserted automatically.

The pipeMAC, pm1000, is designed for streaming data. Received packets are
available immediately with status bits to indicate packet start, end, and CRC error.
Packets may be sent with specified inter-packet gaps and transmission started
as soon as desired, before all data is written into the send Fifo.

The halfMACs, hm1000, are half of a normal MAC. They are receive only or send only.
A dumb device, such as a video camera, may only need to send. For devices which
only need 1 way communication, HalfMACs save gates and rams, precious FPGA
resources.

HalfMACs also separate a MAC into 2 modules. This allows flexibility in FPGA
partitioning. The receive side logic may not be anywhere close to the send side logic.
By separating a MAC into 2 modules, flexibility in placement and pin assignment is
achieved. This can make a big difference with tight designs.

The 100Mb/s MAC & 1000 Mb/s cores with 128 byte Fifos have gate count of less
than 14,000 gates and uses no block rams. The Fifos are created out of LUTs.

The 100Mb/s MAC & 1000Mb/s cores with 2K byte Fifos have gate count of less than
5,000 gates and uses 2 block rams.

The 100Mb/s MAC operates in 100Mb/s full duplex mode only. The 1000Mb/s MAC
operates in 1000Mb/s full duplex mode only. PHY control interface is not included
although available. PHYs almost always power up in the desired mode so no
additional configuration is necessary. RMII interface, which is not standardized and
must be tailored to the specific PHY, is also available.

Conforms to IEEE 802.3-2002 specification, 100Base-TX, 1000BASE-TX full
duplex.
Interfaces to standard PHYs with 4/8 bit wide data busses, MII.
Optional unlimited receive packet size.
Optional source address extraction.
Optional receive packet CRC bytes extraction.
Very simple send & receive FIFO interface.
Support Multicast, Broadcast. No limit on type field.
No MII management interface needed.
Pass through MAC control frames.

Resource usage will vary depending on the actual design.

SM100-128 - 128 byte Fifos 100 Mb/s Ethernet MAC
Number of occupied Slices:                       374
Total Number 4 input LUTs:                      592
Total equivalent gate count for design: 13,855

SM100-2K    - 2K byte Fifos 100 Mb/s Ethernet MAC
Number of occupied Slices:                          289
Total Number 4 input LUTs:                         440
Number of RAMB16s:                                       2
Total equivalent gate count for design:    4,721

SM1000-128 - 128 byte Fifos 1000 Mb/s Ethernet MAC
Number of occupied Slices:                           349
Total Number 4 input LUTs:                          574
Total equivalent gate count for design:   13,694

SM1000-2K    - 2K byte Fifos 1000 Mb/s Ethernet MAC
Number of occupied Slices:                          266
Total Number 4 input LUTs:                         410
Number of FIFO16/RAMB16s:                           2
Total equivalent gate count for design:    4,680

PM1000-2K    - 2K byte Fifos 1000 Mb/s Ethernet MAC
Number of occupied Slices:                          310
Total Number 4 input LUTs:                         510
Number of FIFO16/RAMB16s:                          4
Total equivalent gate count for design:    5,200

HM1000-2K    - 2K byte Fifos 1000 Mb/s Ethernet MAC
Number of occupied Slices:                          200
Total Number 4 input LUTs:                         300
Number of FIFO16/RAMB16s:                           2
Total equivalent gate count for design:    3,000

HM100-2K    - 2K byte Fifos 100 Mb/s Ethernet MAC
Number of occupied Slices:                          170
Total Number 4 input LUTs:                         250
Number of FIFO16/RAMB16s:                           1
Total equivalent gate count for design:    2,500