ChipEnet.com - Real Time Ethernet Switch, MAC, IEEE 1588 clock,
DDR Memory Controller IP cores for Xilinx FPGAs
DDR Memory Controller IP cores for Xilinx FPGAs
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Welcome to ChipEnet, the home of Real Time Ethernet
ChipEnet Inc. offers a variety of Ethernet related FPGA IP cores for applying Ethernet to real time
applications.
Ethernet is ideal for interfacing to your FPGA based design. Whether for debugging, configuration, data
transfer, control, or status, adding a ChipEnet Ethernet MAC(Media Access Controller) to your FPGA design
will allow easy high speed interfacing to the design from a PC or server host, directly or through a switch.
As a switch fabric, Ethernet offers unmatched combination of low cost, low latency, and high sustained
bandwidth for connecting devices and systems. Ethernet is the ideal framework for delivering streaming
audio and video stream, acquiring data from and controlling sensor arrays, providing common shared
resources, and connecting systems for parallel processing.
Read More.
$49 FPGA board with 500 MBytes/sec IO bandwidth. More
Take a look at the video of the $49 FPGA board. http://www.youtube.com/watch?v=IwqSTxiqsng
Current Available IP cores - updated on September 30, 2011
New! Custom MACs
What is a custom MAC ?
A custom MAC is an Ethernet Media Access Controller with additional logic.
Once configured, the MAC performs the desired operations automatically.
Full wire speed rate is sustained with low latency. No processor involvment
is needed.
Why a custom MAC ?
A custom MAC improves efficiency and delivers performance at low cost.
A MAC on the RX side is the first place where a packet can be examined
on a logical basis, so it is the ideal place to perform 1st order
timestamping, filtering and extraction. Since the entire packet is
visible to the MAC, any and all layers of protocol, addresses, and ports
can be examined. Decisions based on packet boolean logic, past history,
external inputs and time can be carried out at wire speed. Processed
packet data can be classified and stored in different Fifos or Rams.
This initial processing greatly reduce the network overhead of
downstream logic and processors.
A MAC on the TX side is the last place where a legal Ethernet packet can
be created. Letting the MAC create the packet removes the networking
overhead from upstream logic & processors, allowing them to focus on
the data in its native state. A ChipEnet MAC can create packets with
any number of layers of protocols, compute checksums, and generate CRC
at full wire speed. Headers can be generated based on dynamic inputs,
real-time clock, boolean logic, and arithmetic operations
What are some examples of custom MACs ?
IEEE 1588 MAC - timestamp arriving packets
- timestamp departing packets
- generate IEEE 1588 packets
- extract parameters from arriving IEEE 1588 packets
IP MAC - generate complete IP headers, IPV4 or IPV6
- generate header checksum
- update sequence ID
UDP MAC - generate complete IP header + UDP header
- generate IP and UDP header checksum
New! IP QoS Switch/Router Features
- Scalabel number of Ports - Gigabit Ethernet - RGMII, SGMII
- IPV4 or IPV6
- QoS for specific flows and Traffic class and packet type
- Scalable number of Priority Queues per port
- Scalable size of Priority Queues per port
- Guaranteed buffer space for high priority packets, no packet loss
- Full wire speed processing for address lookup and QoS
- Low latency cut through capability - under 500ns
- Processor - uBlaze included, others on request
- DDR1/2/3 Ram interface
- Spartan or Virtex implementation
ChipEnet System Memory Controller
- The most advanced DDR memory controller IP core available.
- Power aware with latency and bandwidth optimization. More
IEEE 1588 clock IP cores - version 1 and version 2. More
- complete Master and Slave clocks. No processor or software needed.
- works with any 100Mb or Gb Ethernet PHY
- no special clock oscillator required, default is PHY clock
- Very robust. Tolerate packet delays and drops
- always monotonically increasing
NEW ! Check out the video of the IEEE 1588 clock in action.
http://www.youtube.com/watch?v=GtFxeJHJSLM
Ethernet Switch IP cores. More
- 10/100 Mb or Gigabit Ethernet cut through switches, latency under 250ns
- optional x4 links for speed up to 4 Gb/s
- unmanaged and managed switches
- Multicast and priority switching
- VLAN, IGMP, RSTP/STP support
- Optional IEEE 1588 boundary, End to End, Peer to Peer clock support
ECX Serial Link IP cores. More
- High efficiency, High sustained bandwidth, Fixed latency Fieldbus
120 MBytes/sec from Gb Ethernet,
12 MBytes/sec from 100Mb Ethernet
- 100Mbit and Gigabit versions
- optional x4 links for speed up to 4 Gb/s
- Ideal for streaming video and audio data, either receiving from cameras or serving to
monitors/displays
- Perfect for volume data acquisition and sensor array control
- Optional IEEE 1588 compatible clocks
- fixed delay, low jitter, low latency Ethernet based interconnect
- implement Reflective Memory for use as cluster interconnect
simple programming, usage model - just read and write
- Most efficient backbone for ATA over Ethernet
Ethernet 10/100Mb and Gigabit MAC IP cores. More
- 10/100 Mb, Gb Ethernet versions
- streaming data support
- block data store and forward support
- IEEE 1588 timestamp module available
- Fifo interface, SPI interface, SGMII interface
Ask about our hybrid Circuit and Packet mode Switch IP core
- Ethernet Switch that can work in circuit switched mode and packet switched mode
- Bandwidth allocated per connection
- Circuit switched mode for Isochronous streaming data
- Packet switched mode for random block data
- Ideal for voice or video conferencing or transaction networks
- zero switch delay in circuit switched mode
- link speed up to 4 Gb/s
ChipEnet Inc. offers a variety of Ethernet related FPGA IP cores for applying Ethernet to real time
applications.
Ethernet is ideal for interfacing to your FPGA based design. Whether for debugging, configuration, data
transfer, control, or status, adding a ChipEnet Ethernet MAC(Media Access Controller) to your FPGA design
will allow easy high speed interfacing to the design from a PC or server host, directly or through a switch.
As a switch fabric, Ethernet offers unmatched combination of low cost, low latency, and high sustained
bandwidth for connecting devices and systems. Ethernet is the ideal framework for delivering streaming
audio and video stream, acquiring data from and controlling sensor arrays, providing common shared
resources, and connecting systems for parallel processing.
Read More.
$49 FPGA board with 500 MBytes/sec IO bandwidth. More
Take a look at the video of the $49 FPGA board. http://www.youtube.com/watch?v=IwqSTxiqsng
Current Available IP cores - updated on September 30, 2011
New! Custom MACs
What is a custom MAC ?
A custom MAC is an Ethernet Media Access Controller with additional logic.
Once configured, the MAC performs the desired operations automatically.
Full wire speed rate is sustained with low latency. No processor involvment
is needed.
Why a custom MAC ?
A custom MAC improves efficiency and delivers performance at low cost.
A MAC on the RX side is the first place where a packet can be examined
on a logical basis, so it is the ideal place to perform 1st order
timestamping, filtering and extraction. Since the entire packet is
visible to the MAC, any and all layers of protocol, addresses, and ports
can be examined. Decisions based on packet boolean logic, past history,
external inputs and time can be carried out at wire speed. Processed
packet data can be classified and stored in different Fifos or Rams.
This initial processing greatly reduce the network overhead of
downstream logic and processors.
A MAC on the TX side is the last place where a legal Ethernet packet can
be created. Letting the MAC create the packet removes the networking
overhead from upstream logic & processors, allowing them to focus on
the data in its native state. A ChipEnet MAC can create packets with
any number of layers of protocols, compute checksums, and generate CRC
at full wire speed. Headers can be generated based on dynamic inputs,
real-time clock, boolean logic, and arithmetic operations
What are some examples of custom MACs ?
IEEE 1588 MAC - timestamp arriving packets
- timestamp departing packets
- generate IEEE 1588 packets
- extract parameters from arriving IEEE 1588 packets
IP MAC - generate complete IP headers, IPV4 or IPV6
- generate header checksum
- update sequence ID
UDP MAC - generate complete IP header + UDP header
- generate IP and UDP header checksum
New! IP QoS Switch/Router Features
- Scalabel number of Ports - Gigabit Ethernet - RGMII, SGMII
- IPV4 or IPV6
- QoS for specific flows and Traffic class and packet type
- Scalable number of Priority Queues per port
- Scalable size of Priority Queues per port
- Guaranteed buffer space for high priority packets, no packet loss
- Full wire speed processing for address lookup and QoS
- Low latency cut through capability - under 500ns
- Processor - uBlaze included, others on request
- DDR1/2/3 Ram interface
- Spartan or Virtex implementation
ChipEnet System Memory Controller
- The most advanced DDR memory controller IP core available.
- Power aware with latency and bandwidth optimization. More
IEEE 1588 clock IP cores - version 1 and version 2. More
- complete Master and Slave clocks. No processor or software needed.
- works with any 100Mb or Gb Ethernet PHY
- no special clock oscillator required, default is PHY clock
- Very robust. Tolerate packet delays and drops
- always monotonically increasing
NEW ! Check out the video of the IEEE 1588 clock in action.
http://www.youtube.com/watch?v=GtFxeJHJSLM
Ethernet Switch IP cores. More
- 10/100 Mb or Gigabit Ethernet cut through switches, latency under 250ns
- optional x4 links for speed up to 4 Gb/s
- unmanaged and managed switches
- Multicast and priority switching
- VLAN, IGMP, RSTP/STP support
- Optional IEEE 1588 boundary, End to End, Peer to Peer clock support
ECX Serial Link IP cores. More
- High efficiency, High sustained bandwidth, Fixed latency Fieldbus
120 MBytes/sec from Gb Ethernet,
12 MBytes/sec from 100Mb Ethernet
- 100Mbit and Gigabit versions
- optional x4 links for speed up to 4 Gb/s
- Ideal for streaming video and audio data, either receiving from cameras or serving to
monitors/displays
- Perfect for volume data acquisition and sensor array control
- Optional IEEE 1588 compatible clocks
- fixed delay, low jitter, low latency Ethernet based interconnect
- implement Reflective Memory for use as cluster interconnect
simple programming, usage model - just read and write
- Most efficient backbone for ATA over Ethernet
Ethernet 10/100Mb and Gigabit MAC IP cores. More
- 10/100 Mb, Gb Ethernet versions
- streaming data support
- block data store and forward support
- IEEE 1588 timestamp module available
- Fifo interface, SPI interface, SGMII interface
Ask about our hybrid Circuit and Packet mode Switch IP core
- Ethernet Switch that can work in circuit switched mode and packet switched mode
- Bandwidth allocated per connection
- Circuit switched mode for Isochronous streaming data
- Packet switched mode for random block data
- Ideal for voice or video conferencing or transaction networks
- zero switch delay in circuit switched mode
- link speed up to 4 Gb/s