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Ethernet is the ideal HW & SW solution for interfacing to your FPGA based system.
Whether for debugging, configuration, data transfer, control, or status, adding a
ChipEnet Ethernet MAC(Media Access Controller) to your FPGA design will allow easy
high speed interfacing to the FPGA from a PC or server host, directly or through a
switch. No TCP/IP or UDP processing needed !!!

An Ethernet MAC offers a wonderfully simple interface abstraction. A stream of bytes
goes into the MAC and then magically shows up at the output of another MAC. What
is contained in this stream of bytes is up to you. It can be data or control in any
format you desire. This stream of bytes can be processed by FPGA logic or by a
software program with the addition of a few lines of code. A ChipEnet MAC adds a
very useful capability to your FPGA design quickly and at low costs.

ChipEnet Ethernet MACs are specifically designed for FPGAs

		Low gate/LUT count, low as 5,000 gates. read more
		Simple HW interface. read m or e
		Simple SW interface - C sample code provided. read m or e
		No driver programming needed. read m or e
		Windows, Linux, Unix supported. read m or e
		Easy licensing - project or site licenses. No royalties. read m or e
		Self contained diagnostic logic provided. Be up and running in your FPGA in as
		little as 30 minutes after receiving the design package. read m or e

4 Gb/s Ethernet

As of this writing, May 2006, 10 Gb Ethernet is still in its infancy.
Components such as PHYs & connectors are expensive and signal integrity
issues are challenging. The easy and cost effective solution to higher
bandwidth Ethernet is to group together 1 Gb Ethernet MACs, PHYs,
connectors and cables to form a higher bandwidth virtual Ethernet link. This
idea is not new and is presently used in the x4, x8, etc versions of PCI
Express as well as Infiniband.

Grouping together four ChipEnet SM1000 Gigabit Ethernet MACs results in a
low gate count, low pin count, and very compatible 32 bit data width virtual 4
Gb/s Ethernet MAC.

For more details, the application note is here.

Linux Packet Processing Limits

In the course of characterizing the SM1000 Gigabit MACs, some interesting
measurements of Linux Ethernet packet processing bandwidth were made.

The test setup consists of a Dell PowerEdge 1400SC server with a 993 MHz
processor and 768 MB of memory. The OS is Linux 2.4 in a standard Red Hat
distribution. No changes were made to the default installation. The internal
Gigabit NIC was directly attached to the SM1000 Ethernet MAC inside of a
Xilinx Virtex 4 FPGA. The FPGA also contained a programmable packet
generator which automatically generated sequentially numbered packets at a
selected rate. The packets were 98 bytes in length. The packets were
received using raw socket and checked for dropped packets using the packet
sequence numbers. No other software was running besides Linux and the
test code.

The test procedure is to select a packet generation rate, start the packet
generator and the test software and generate 1 million packets. The test
software logged the dropped packets, if any. Each run is 1 million packets.

The results are:

211 packets/sec No errors in all runs.

238 packets/sec 2 consecutive packets dropped in 1 run
                  4 consecutive packets dropped in 1 run
                  No packets dropped in some runs.

273 packets/sec 20 consecutive packets dropped in 1 run
                  40 consecutive packets dropped in 1 run.
                  68 consecutive packets dropped in 1 run
                  20 consecutive packets dropped in 1 run.
                 152 consecutive packets dropped in 1 run.

What do the results mean ?

The results show that Linux 2.4 on this specific Dell machine can handle a
maximum of about 210 packets/sec, each packet being 98 bytes in size,
without dropping packets. Above 250 packets/sec, Linux can't respond to all
incoming packets and start dropping large groups of packets.

If there were other more demanding applications running at the same time,
the best possible packet handling rate would be even lower.

Gigabit Ethernet is capable of delivering a large amount of packets. Any
particular HW and SW combination that needs to process packets reliably
should be characterized with respect to rate of packet arrival to make sure
the HW and SW design can handle the workload.