$49 FPGA board with 500 MBytes/sec IO bandwidth
The above photo shows a $49 FPGA board with 500 MBytes of IO bandwidth. This FPGA board
consists of an Avnet Spartan-3A evaluation board with an attached dual Ethernet Gb PHY daughter
card wired to the 40 pin IO expansion header of the base FPGA board. Avnet sells the base FPGA
board for $49 and it comes with ISE 10 programming software and USB programming cable. The
board has a 400K gates Xilinx Spartan-3A fpga, a Cypress PSoC mixed signal array chip which
handles the USB interface and can also serve as an A/D convertor, a TI digital temperature sensor,
a Spansion flash memory chip, a 40 pin (36 usable) header with 100 mil spacing, and assorted other
stuff. This FPGA board is the best deal right now for a low cost fpga board.
Take a look at the video of the $49 FPGA board.
http://www.youtube.com/watch?v=IwqSTxiqsng
Thanks Avnet !!!
The daughter card contains two Ethernet Gb PHY chips, two RJ45 jacks, two voltage translator
chips, and a linear regulator. The daughter card is simply wired to the 40 pin header of the
base board. The two PHYs provide 2 receive channels running at 125 MBytes/sec each and 2
transmit channels also running at 125 MBytes/sec each, thus providing 500 MBytes/sec of full duplex
IO bandwidth. The PHYs interface to the FPGA MACs via RGMII interfaces. So each channel bit is
operating at 250 Mbits/sec using DDR data with the 125 Mhz clocks. All 4 channels are independent.
All signals are single ended. The PHYs allow connection distances up to 100 meters.
Frankly I wasn't sure at all this daughter card would work. Having read too many
PDN( Power Distribution Network) and signal integrity papers, it didn't seem possible that
such a simplistic design can possibly work. No termination resistors are used, no spice simulation
was performed, and the traces are obviously grossly mismatched in impedance. Of course, the signal
topology is very simple, short ( less than 3 inches ) unidirectional point to point connections. The
signals look surprisingly good in the critical transition range. There are
overshoot and undershoot but the threshold crossings are fast and clean.
The Spartan-3A FPGA can easily handle 125 Mhz logic with the standard ISE 10 settings. A few
clicks and the design bit file is ready for download. No special optimization is required,
no careful laborious manual placement or editing of the LUTs are needed. The 400K gates rated
FPGA is small by current FPGA standards but >100K gates is still a lot of logic. Mainframe computers
used to have less than 400K gates with much less than 500 MBytes of IO bandwidth and yet served
thousands of users. Of course, that was before the prevalence of layers of interpreted APIs and
flashy GUIs.
consists of an Avnet Spartan-3A evaluation board with an attached dual Ethernet Gb PHY daughter
card wired to the 40 pin IO expansion header of the base FPGA board. Avnet sells the base FPGA
board for $49 and it comes with ISE 10 programming software and USB programming cable. The
board has a 400K gates Xilinx Spartan-3A fpga, a Cypress PSoC mixed signal array chip which
handles the USB interface and can also serve as an A/D convertor, a TI digital temperature sensor,
a Spansion flash memory chip, a 40 pin (36 usable) header with 100 mil spacing, and assorted other
stuff. This FPGA board is the best deal right now for a low cost fpga board.
Take a look at the video of the $49 FPGA board.
http://www.youtube.com/watch?v=IwqSTxiqsng
Thanks Avnet !!!
The daughter card contains two Ethernet Gb PHY chips, two RJ45 jacks, two voltage translator
chips, and a linear regulator. The daughter card is simply wired to the 40 pin header of the
base board. The two PHYs provide 2 receive channels running at 125 MBytes/sec each and 2
transmit channels also running at 125 MBytes/sec each, thus providing 500 MBytes/sec of full duplex
IO bandwidth. The PHYs interface to the FPGA MACs via RGMII interfaces. So each channel bit is
operating at 250 Mbits/sec using DDR data with the 125 Mhz clocks. All 4 channels are independent.
All signals are single ended. The PHYs allow connection distances up to 100 meters.
Frankly I wasn't sure at all this daughter card would work. Having read too many
PDN( Power Distribution Network) and signal integrity papers, it didn't seem possible that
such a simplistic design can possibly work. No termination resistors are used, no spice simulation
was performed, and the traces are obviously grossly mismatched in impedance. Of course, the signal
topology is very simple, short ( less than 3 inches ) unidirectional point to point connections. The
signals look surprisingly good in the critical transition range. There are
overshoot and undershoot but the threshold crossings are fast and clean.
The Spartan-3A FPGA can easily handle 125 Mhz logic with the standard ISE 10 settings. A few
clicks and the design bit file is ready for download. No special optimization is required,
no careful laborious manual placement or editing of the LUTs are needed. The 400K gates rated
FPGA is small by current FPGA standards but >100K gates is still a lot of logic. Mainframe computers
used to have less than 400K gates with much less than 500 MBytes of IO bandwidth and yet served
thousands of users. Of course, that was before the prevalence of layers of interpreted APIs and
flashy GUIs.
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