ChipEnet System Memory Controller
The ChipEnet System Memory Controller, CSMC, IP core is, hands down, the most advanced
synchronous DRAM controller available. It will handle read and write requests from multiple ports and
execute the operations such that power consumption of the DRAMs is minimized while reducing the
latency of execution and maintaining data integrity.

The modern synchronous, SD/DDR/DDR2/DDR3, DRAM can be viewed as a giant array of capacitors
which can charge and discharge at a very high rate. While each individual capacitor has very small
capacitance, there are hundreds of million or billions of these capacitors in each DRAM chip and a large
subset of them may be charged and discharged for each DRAM command. Current surges of
hundreds of milliamps or even amps over a period of tens of nanoseconds can occur in an array of
DRAMs. This simple reality lies at the core of power management and signal integrity issues  with
synchronous DRAMs. CSMC understands this reality and the specifics of the DRAMs being controlled,
via the DRAM configuration, and executes the read, write and refresh operations with minimal
switching of the DRAM capacitor arrays.

The second unique aspect of the modern synchronous DRAMs is the high data bandwidth possible. A
DDR DRAM in full flight delivers data at rates easily matching the fastest bipolar SRAMs of previous
generations. Unfortunately, this high data bandwidth is accompanied by long pipelines with complex
interactions and long startup delays.  Thus achieving high effective data bandwidth and minimizing
latency of command completion requires as much effort as extracting performance from a CDC Cyber  
205 vector supercomputer of  the 80s. CSMC performs out of order reads and writes to maximize
data bandwidth and recognize priority of requests to reduce latency to request completion.

Address mapping of request address to specific DRAM bytes is crucial to sustained performance.  A
suitable mapping guarantees conflict free access for maximum performance while a poor mapping
limits the actual memory system performance to a fraction of the potential. While compilers and
algorithm design can have substantial impact on memory system performance, the fixed address
mapping of conventional memory controllers limit the possibilities. CSMC supports the usage of
different address mapping for different portions of the address space. The switch to different address
mapping can be done on a per request basis. This ability means every process can have optimum
conflict free access to memory for best possible performance.

The third consideration for memory system design is error detection and correction. Traditionally, a
Hamming code is used to correct single bit errors, some double bit errors and detect errors. The
additional ECC bytes are placed in a separate ram. This approach is fast, reasonably easy to
implement and offers good memory integrity. This is still a good approach for memory systems
implemented with multiple concurrently accessed DRAMs. However, modern synchronous DRAMs have
changed the design space. Synchronous DRAMs have the following characteristics:

  • Large amounts of data per chip
  • Large amounts of data per row access
  • Excellent reliability - millions of desktop PC with no ECC
  • Very low cost per byte
  • Very high burst data bandwidth
  • High power consumption per row access - reads always mandate a write

These characteristics encourage having data words concentrated in one DRAM chip rather than
scattered across many DRAM chips. Depending on the failure mode, a single fault may destroy many
data bits, much more than any fast error correcting code can recover from. Of course, bad bits are
not always due to internal DRAM flaws. Power distribution network decoupling capacitors age and
change their capacitance or fail and this can impact correct data access due to the high switching
currents. A PCB design that works correctly when  first tested may not work correctly under some
conditions when board components are later changed, creating new signal integrity stress cases.  

Interestingly, DRAM data access have now come to resemble network packets with their bursty
nature. With Ethernet packets, CRC bytes for error detection and retry for error correction is the
proven method for reliable operation. This suggests that a single CRC byte appended to a "line" of
DRAM data may be a suitable approach to error detection with retry or error concealment as the
correction mechanism. The low cost and high capacity of DRAMs also suggest redundancy as a
suitable approach for fast error correction.

This is a brief summary of the architectural and design considerations that have gone into the CSMC.
Feel free to contact  james.ma@chipenet.com to continue the discussion.